A common requirement for an advanced electronic circuit and particularly for circuits manufactured as integrated circuits (“ICs”) in semiconductor processes are the use of memory for storage, and more recently, for discrete memory. Memory cells may be dynamic RAM (“DRAM”) or faster cells such as static random access memory (“SRAM”). In some highly integrated devices, embedded memory arrays are provided as part of an integrated circuit that may include additional functionality. So called systems on a chip (“SoC”) devices may provide a processor, program memory, data storage memory, and other functions needed to implement an entire system solution. Single chip cellphones, PDAs, etc. are possible using SoC technology. These advanced integrated circuits require embedded SRAM memory formed as part of an integrated circuit that also includes other functions, such as analog to digital converters, radio transceivers, microprocessors, microcontrollers, processors, cell phone circuitry and the like. Recently, the embedded memory designs are sometimes provided as “cores” or “macros” that are included with other user specified functionality circuits on an integrated circuit such as an application specific integrated circuit (“ASIC”).
Memory arrays may be formed with an array of SRAM cells arranged to place stored charge representing data onto one of, or a pair of, bit lines. These bit lines may also be referred to as digit lines or column lines. The bit lines are coupled to the stored values in the cells in response to a signal on an active row line, which may also be referred to as a word line. The bit lines carrying the data are then coupled to sense amplifiers. Sometimes differential sense amplifiers are used that receive a relatively small differential voltage signal, typically a differential voltage signal across a pair of true and complement bit lines, and in that case the sense amplifier then latches the sensed value, outputting an amplified data signal for use by other circuits. This amplified signal may have a full logic level voltage of 1.0 volts or greater for a high level, and nearly zero volts or ground for a low level. A data value is represented by this voltage level, which may be a “1” or a “0” for binary data. The data value may be arbitrarily assigned one or another voltage level, and no direct correspondence is necessary.
In an SRAM array, when a write cycle is performed, a row or word line coupled to the selected row of cells is activated. The row selection is done by decoding a portion of a memory address field, in a so called “row decoder”. This write word line may cause columns of memory cells that are not selected for the write operation to have their internal storage nodes coupled to the corresponding bit lines. Because these cells are not selected to receive new data, but are sometimes affected by write operation due to the write word line going active, they are referred to as “half selected” cells. The half selected cells may be affected by a “cell disturb” effect, that is, because pass gates are typically used in the write portion of these SRAM cells, and the active word line causes these pass gates to open, the data stored inside the cells may be erroneously changed, and a “cell disturb error” may occur. TCell disturb should be avoided.
In conventional SRAM arrays, a single read port may be used with an SRAM cell. Single read port SRAM cells are compact in area and thus, provide relatively good circuit density, which is desired in memory arrays and in embedded memory arrays.
This single read port may be used to overcome the “half select” effect. However, in order to do prevent the cell disturb that might otherwise occur, when a write is performed to a cell in a selected column, a read cycle and then a write back cycle is performed to cells in unselected columns. The time required to read the unselected cells that are positioned along the active write word line, and then the time required put the retrieved data into a write circuit, and write it back to the unselected SRAM cells, is undesirably long. The use of a single read port means that the cell read time is extended in order for the single ended read bit line to reach the full logic level voltage, and then the read data is treated as write data for the unselected columns, and then subsequently written back to the unselected cells. During the write back, the selected cell is also written with the incoming write data, but that cell is fully selected and therefore not subject to the “half select” disturb errors. Use of the read write back to prevent the “half select” disturb errors in the conventional SRAM array requires an extra long write cycle, and this then slows the data throughput of the device.
A continuing need thus exists for an SRAM array and sense amplifier circuitry that provides a faster write cycle including a read write back for the unselected column cells, so that the write cycles do not need to be extended in time in order to address the “half select” disturb of unselected cells.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.